A typical structure of an MIS-type field effect transistor is provided with source and drain regions formed in a major surface portion of a semiconductor substrate in such a manner as to be spaced apart from each other by a channel region on which a gate insulator and a gate electrode are laminated for formation of a gate structure. The MIS-type field effect transistor thus formed has the source and drain regions and the channel region substantially coplanar with one another. As a result, impurity atoms are first implanted into the channel region for adjusting the threshold voltage thereof, which is followed by the formation of the gate structure consisting of the gate insulator and the gate electrode by using an appropriate lithography technique. Then, another ion implantation is carried out for formation of the source and drain regions using the gate structure as a mask. Using this process sequence, the threshold voltage should be adjusted before the determination of the channel length decided by the formation of the source and drain regions.
However, a problem is encountered in the prior art since the production yield deteriorates. This is because of the fact that a threshold voltage drift tends to take place due to the irregularity of the channel length of the MIS-type field effect transistor. If the MIS-type field effect transistor is designed to have a relatively short channel, the short-channel effect is liable to take place thus causing the irregularity of the channel length to strongly influences the drift of the threshold voltage. When the drift of the threshold voltage exceeds a predetermined range, the MIS-type field effect transistor is rejected as an inferior transistor, thereby diminishing the production yield. In the semiconductor manufacturing field, production yield is an extremely important factor in reducing the device cost, so that a solution has been sought to increase the production yield of the MIS-type field effect transistor.